Title :
VLSI architecture for discrete wavelet transform
Author :
Grzeszczak, A. ; Yeap, T.H. ; Panchanathan, S.
Author_Institution :
Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
Abstract :
This paper presents a new VLSI architecture for computing the discrete wavelet transform (DWT). The architecture is systolic in nature and utilizes a frequency doubler, which enables it to perform all coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature. The architecture is simple, modular, and cascadable, and hence can be implemented in VLSI
Keywords :
VLSI; digital signal processing chips; image processing; systolic arrays; wavelet transforms; VLSI architecture; cascadable architecture; coefficient calculations; discrete wavelet transform; frequency doubler; image processing; modular architecture; multipliers; systolic architecture; Digital signal processors; Image processing; Systolic arrays; Very-large-scale integration; Wavelet transforms;
Conference_Titel :
Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-2416-1
DOI :
10.1109/CCECE.1994.405788
