Title :
Minimizing the Routing Cost During Logic Extraction
Author :
Hirendu Vaishnav, Massoud Pedram
Author_Institution :
Department of EE - Systems, University of Southern California, Los Angeles, CA
Abstract :
This paper describes techniques for reducing the routing cost during logic extraction. Two routing cost functions derived from the global structure of a boolean network are analyzed and the effectiveness of each cost function is compared against the conventional literal savings cost function. Experimental results obtained with these routing cost functions are presented and discussed in detail.
Keywords :
CMOS logic circuits; CMOS technology; Circuit synthesis; Contracts; Cost function; Delay estimation; Minimization; Phase measurement; Routing; Timing;
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-89791-725-1
DOI :
10.1109/DAC.1995.250066
