DocumentCode :
3162165
Title :
Optimal Low Power Design of DDR2 Memory Interface for Compact Ultra Mobile Personal Computer (UMPC) Applications
Author :
Lee, JB ; Ahn, Seungyoung ; Yoon, Seungjoon ; Chun, Jongtae
Author_Institution :
Samsung Electron, Suwon
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
922
Lastpage :
925
Abstract :
In this paper, we suggest a topology design optimization of the address/command signals for DDR2 memory module to minimize the overshoot in waveforms when the 0.9V VTT terminations are removed for power saving and cost reduction. Simulations in frequency domain and time domain are performed for optimal signal integrity, and the optimized designs are verified by measurements.
Keywords :
DRAM chips; integrated circuit design; low-power electronics; network topology; DDR2 memory interface; address signal; command signal; compact ultra mobile personal computer; cost reduction; frequency domain; optimal low power design; power saving; time domain; topology design optimization; Application software; Computational modeling; Cost function; Design optimization; Frequency domain analysis; Microcomputers; Mobile computing; Performance evaluation; Signal design; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-1323-2
Electronic_ISBN :
978-1-4244-1323-2
Type :
conf
DOI :
10.1109/EPTC.2007.4469801
Filename :
4469801
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3162165
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