Reliability analysis of a fault-tolerant multi-bus multiprocessor system

The paper proposes a fault-tolerant multi-bus system called binomial multi-bus architecture and analyses its reliability using a combinatorial method involving unreliability and mutually exclusive partitioning. Some attractive features of this architecture include low interconnection complexity, and a high degree of fault-tolerance. It is found that the probability of bus survival has a greater influence on the system reliability than the processors or memory modules. Comparison with the fully connected multi-bus architecture shows an important result, i.e. at least one-third of the connection cost is reduced at the expense of only a very slight decrease in the system reliability. Thus, the proposed architecture exhibits a strong potential to be a cost-effective interconnection network