A Novel Parasitic-Aware Synthesis and Verification Flow for RFIC Design

The design of radio-frequency integrated circuits (RFICs) is highly sensitive to layout parasitics. In conventional methodologies, the layout parasitics are known only after the layout is complete and the schematic is resized to compensate for these parasitics. The drawback of such a methodology is that the convergence of this design iteration remains unpredictable. This paper proposes a novel synthesis and verification flow for RFIC designs. The design flow is composed of three stages: circuit sizing with floorplan, performance-aware floorplan refinement, and full-wave electromagnetic (EM) extraction. Layout parasitics are considered throughout the design flow in the proposed methodology. As a result, parasitic closure can be achieved quickly and design iterations may not be required. As an example, the proposed design flow is applied to a cross-coupled inductance-capacitance (LC) VCO. Demonstrating the efficiency of the proposed flow for RFIC designs, it required only two weeks to meet all the design specifications with no iterations