DocumentCode :
3162328
Title :
On Test Set Preservation of Retimed Circuits
fYear :
1995
fDate :
1995
Firstpage :
176
Lastpage :
182
Abstract :
Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a pre-determined number of arbitrary input vectors. Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.
Keywords :
Circuit faults; Circuit testing; Graphics; Integrated circuit synthesis; Laboratories; Optimization; Registers; Sequential circuits; Synchronization; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.250086
Filename :
1586698
Link To Document :
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