Simultaneous switching noise suppression for high speed systems using embedded decoupling

High performance computing systems are driving towards higher clock speeds, more switching circuits, and lower operating voltages. Simultaneous switching noise (SSN) will greatly affect signal integrity in such complex future mixed signal systems. It has been reported that in addition to inductance effects, power plane bounce also becomes a critical factor for packages containing many power and ground vias in parallel. Discrete surface mount capacitors are currently being used by designers to suppress noise. As part of the System on a Package (SOP) concept being developed at the Packaging Research Center (PRC), Georgia Tech, a test vehicle to demonstrate the suppression of SSN using embedded decoupling capacitors is being implemented. This test vehicle uses thin film sequential buildup technology on a low-cost organic platform incorporating polymer-ceramic nanocomposite dielectrics. The design rules for the test vehicle were developed using SOP substrate materials and processes; furthermore, Ansoft along with Matlab were used to model the microstrip transmission lines. The layout was done using Cadence Advanced Package Designer (APD) and output into Gerber format for fabrication. The current test vehicle uses a 300 mm ×300 mm high T_g FR-5 base substrate with four metal layers on each side. Photoimageable epoxy dry films of 25 μm and 75 μm thickness were used as the low k (3.4-3.9) sequential build-up dielectric. A novel photoimageable polymer ceramic nanocomposite material developed at the PRC was used for the high k (25-50) thin films. Low cost materials and large area processes were used for the substrate fabrication including dry film printed wiring board (PWB) photoresists, vacuum lamination and spin/meniscus coating for dielectric deposition, full-field UV lithography, and electroless and electrolytic copper metallization. Simulations confirm that the SSN will be suppressed by a factor often when using the high k material as the capacitor dielectric. This paper presents the design, fabrication and validation of embedded decoupling for SOP technology