DFT as test optimization strategy

Summary form only given. This paper describes board and system level Design-for-Testability (DFT) methodology as test optimization strategy. Test engineers take great pain to incorporate DFT principles and rules into their circuitry, but digital paradigm cannot realize the entire spectrum of this methodology. A modem mixed-signal board contains swarms of purely digital ICs, purely analog ICs, as well as complex digital/analog devices and discrete well-known components. On the system level, the most of backplane signals between separate boards are conveys through in differential form (LVDS), because it reduce concerns about noise. LVDS stands for Low Voltage Differential Signalling, and it is the state-of-the-art way to communicate data using a very low voltage swing differentially over two backplane traces. The LVDS interconnections open the new system level test approach with the deployment of IEEE Standard 1149.4 Mixed-Signal Boundary Scan test techniques.