Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation

This paper outlines our successful Concurrent Design Methodology and Configuration Management adopted for a Processor system simulation at both VHDL and GATE level. The complexity of the system simulated was 4 PENTIUMs and 28 ASICs with a total gate count of 2.4 MGates. It has been proven that simulation of such a complex system can be done on VHDL level and the efficiency of finding and correcting errors early in the design cycle was demonstrated.