DocumentCode :
3162523
Title :
Optimization of Reliability of Copper Column Flip Chip Packages with Variable Compliance Interconnects
Author :
Tay, Andrew A O ; Ho, Siow Ling
Author_Institution :
Nat. Univ. of Singapore, Singapore
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
499
Lastpage :
503
Abstract :
This paper describes a parametric study of the reliability of solder joints in wafer level flip chip packages that employ copper column interconnects. In this study, the impact of the change in the compliance of the copper column interconnects on the fatigue life of the solder joints were investigated by varying the diameter of the copper column interconnects. 2-D elastic-plastic finite element analyses were carried out on packages with constant interconnect diameter as well as those with variable interconnect diameters within the same package. The effect of changing the pitch and the pad size were also studied. It was found that an effective strategy in increasing the fatigue life and hence the reliability of the solder joints is by distributing copper columns of lower compliance (greater diameter) near the center of the package and increasing the compliance of the copper columns (decreasing their diameter) towards the perimeter of the chip package. In addition, elastic- plastic-creep analysis was also performed on the packages. It was observed that the results from the elastic-plastic analysis and the elastic-plastic-creep analysis exhibit the same trend.
Keywords :
copper; elasticity; fatigue; finite element analysis; flip-chip devices; integrated circuit interconnections; integrated circuit reliability; plasticity; solders; wafer level packaging; 2D elastic-plastic finite element analyses; copper column interconnects; fatigue life; reliability optimization; solder joints reliability; variable compliance interconnects; wafer level flip chip packages; Copper; Electronics packaging; Fatigue; Finite element methods; Flip chip; Integrated circuit interconnections; Integrated circuit packaging; Parametric study; Soldering; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-1323-2
Electronic_ISBN :
978-1-4244-1323-2
Type :
conf
DOI :
10.1109/EPTC.2007.4469820
Filename :
4469820
Link To Document :
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