High speed digital design

Digital data are routed through a satellite in two disparate forms: through computational processors as 32 bits in parallel (a digital “word”) with a relatively low speed clock rate of about 25 MHz and through intersatellite links as bits in series with a high speed clock rate of about 1 GHz. A high speed digital router spans clock rate gap by combining both classical digital and RF design disciplines. The router implements digital functions while incorporating RF effects. Digital functions include: merging words from multiple sources, converting the data from parallel words into serial bits, rate buffering to synchronize the data, optionally routing data through alternate paths such as cross strapping and/or routing the data to other units and maintaining extremely accurate timing synchronization (under 100 ps). RF effects include amplitude attenuation, rise/fall time degradation and impedance matching. This paper will describe the design of a high speed digital data router consisting of custom ICs and printed circuit boards. ICs implement the digital functions, provide RF signal amplification and source and load impedance matching. PCBs adjust clock and data timing using microstrip and stripline transmission lines matched in length to a few thousandths of an inch