Title :
The Aurora RAM Compiler
Abstract :
This paper describes a RAM compiler for generating and characterizing highly manufacturable optimized SRAMs using GaAs E/D MESFET technology. The compiler uses a constraint-driven design flow to achieve process tolerant RAMs. This compiler was built using a flexible design framework that can be easily adapted to optimize and characterize memories in different MESFET processes.
Keywords :
Circuit noise; Circuit simulation; Delay; Design automation; Gallium arsenide; MESFETs; Optimizing compilers; Pulp manufacturing; Random access memory; Read-write memory;
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-89791-725-1
DOI :
10.1109/DAC.1995.250101
