DocumentCode :
3162684
Title :
Test Program Generation for Functional Verification of PowePC Processors in IBM
fYear :
1995
fDate :
1995
Firstpage :
279
Lastpage :
285
Abstract :
A new methodology and test program generator have been used for the functional verification of six IBM PowerPC processors. The generator contains a formal model of the PowerPC architecture and a heuristic data-base of testing expertise. It has been used on daily basis for two years by about a hundred designers and testing engineers in four IBM sites. The new methodology reduced significantly the functional verification period and time to market of the PowerPC processors. Despite the complexity of the PowerPC architecture, the three processors verified so far had fully functional first silicon.
Keywords :
Automatic programming; Automatic testing; Computational modeling; Permission; Power engineering and energy; Power generation; Predictive models; Silicon; System testing; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.249960
Filename :
1586716
Link To Document :
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