Title :
Pixel cache architecture with FIFO implemented within an ASIC
Author :
Ikedo, Tsuneo ; Ma, Jianhua
Author_Institution :
Comput. Archit. Lab., Aizu Univ., Japan
Abstract :
Implementation technology for 3D pixel cache and performance evaluation of a graphics processor Truga001, with 12 embedded processors within a single chip, are described. The chip can render 4 million vectors/s (10 pixels/vector) or 1.2 million triangle polygons/s (100 pixels/polygon) with Phong shading, texture mapping and hidden surface removal. A pixel-array configured with 8(x)×4(y)×24-bit(intensity)×24-bit(z) can be accessed with frame buffer at 180 ns due to the 3D bus-architecture between chip and frame buffer. The chip was designed with Toshiba TC180C CMOS of 400,000 gates
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; cache storage; computer graphic equipment; digital signal processing chips; hidden feature removal; image texture; parallel architectures; performance evaluation; reduced instruction set computing; rendering (computer graphics); 180 ns; 3D bus architecture; 3D pixel cache; ASIC; DSP chip; FIFO; Phong shading; Toshiba TC180C CMOS; Truga001; frame buffer; graphics processor; hidden surface removal; performance evaluation; pixel cache architecture; texture mapping; Application specific integrated circuits; Buffer storage; Computer architecture; Computer graphics; Laboratories; Logic; Random access memory; Read-write memory; Reduced instruction set computing; Rendering (computer graphics);
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551955
