Computer design strategy for MCM-D/flip-chip technology

Author

Franzon, Paul D. ; Glaser, Alan ; Conte, Tom ; Lipa, Steve ; Banerjia, Sanjeev ; Schaffer, Toby ; Alvo, Scott ; Stanaski, Andrew ; Tekmen, Yusuf

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

35

Lastpage

39

Abstract

A compelling case is made for using MCM-D (thin film MultiChip Module) flip-chip technology to build a `MegaChip´ CPU consisting of an Instruction Fetch Unit and Execution Unit. By building part of the Instruction Fetch Unit in an optimized SRAM process, significant performance/cost gains are made. We also address the following important `implementation´ (1) Partitioning high speed paths across the chip boundary within timing specs; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; (4) Managing test costs; and (5) implementing a debug strategy. This paradigm is also potentially useful for other memory intensive applications, including ATM, etc

Keywords

flip-chip devices; microprocessor chips; multichip modules; Execution Unit; Instruction Fetch Unit; MCM-D; MegaChip CPU; SRAM; computer design; flip-chip technology; thin film multichip module; Buildings; Clocks; Cost function; Energy management; Memory management; Multichip modules; Performance gain; Random access memory; Timing; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551958

Filename

551958