A fast compact addition architecture for low power microprocessors and DSP chips

An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits