A fast compact addition architecture for low power microprocessors and DSP chips

Author

Gayles, Eric S. ; Owens, Robert M. ; Irwin, Mary Jane

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

41

Lastpage

44

Abstract

An addition scheme is presented which has comparable performance to carry-lookahead for the bit precisions required by most microprocessors and DSP chips. The proposed architecture results in adders with regular layout structures, low interconnect complexities, and which occupy little area. Several adders of varying architectures and logic styles were built for comparison with our scheme. Designed with a 3.3 V, 0.5 μm process, at 16-64 bit precisions, our architecture resulted in the lowest energy addition circuits

Keywords

adders; digital signal processing chips; microprocessor chips; 0.5 micron; 3.3 V; DSP chip; adder; addition circuit; carry select architecture; low power microprocessor; Adders; Computer science; Delay; Digital signal processing chips; Integrated circuit interconnections; Logic; Microprocessors; Portable computers; Power dissipation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.551960

Filename

551960