DocumentCode
3162863
Title
Software Accelerated Functional Fault Simulation for Data-Path Architectures
Author
M. Kassab, N. Mukherjee, J. Rajski, J. Tyszer
Author_Institution
Microelectronics and Computer Systems Laboratory, McGill University, Montreal, Canada
fYear
1995
fDate
1995
Firstpage
333
Lastpage
338
Abstract
This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity. This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.
Keywords
Acceleration; Adders; Arithmetic; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer architecture; Logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
0-89791-725-1
Type
conf
DOI
10.1109/DAC.1995.249969
Filename
1586725
Link To Document