Title :
On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits
Author :
Martínez-Smith, Alfoiiso ; Sridhar, Ramalingam
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Abstract :
Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style
Keywords :
CMOS logic circuits; combinational circuits; delays; fault location; integrated circuit testing; logic design; logic testing; pipeline processing; CMOS wave pipelined circuits; delay fault sensing technique; design style; environmentally-induced delay faults; online correction; online detection; random propagation delays; wave pipelined logic gates; CMOS logic circuits; CMOS technology; Circuit faults; Circuit optimization; Electrical fault detection; Fault detection; Logic design; Logic gates; Pipeline processing; Propagation delay;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551963
