Title :
A closed-form solution to the damped RLC circuit with applications to CMOS ground bounce estimation
Author :
Gabara, Thaddeus
Author_Institution :
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
Abstract :
A simplified RLC model depicting a packaged CMOS device is used to determine the fall time of an output buffer. The fall time is dependent on how many outputs are switching simultaneously. The analysis was compared with the measurements of a 0.5 μm CMOS test chip with good results. These results indicate that the fall time of a buffer is determined by the parasitic components in the system (R, L and C) and may not be the same as the intrinsic fall time of the output buffer in an ideal environment, i.e., L=0
Keywords :
CMOS digital integrated circuits; equivalent circuits; integrated circuit modelling; linear network analysis; passive networks; 0.5 micron; CMOS ground bounce estimation; closed-form solution; damped RLC circuit; output buffer fall time; packaged CMOS device; parasitic components; Circuit simulation; Closed-form solution; Equations; Inductance; Packaging; Parasitic capacitance; RLC circuits; Semiconductor device measurement; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551966
