• DocumentCode
    3162927
  • Title

    Analysis of Switch-Level Faults by Symbolic Simulation

  • Author

    Lluis Ribas-Xirgo, Jordi Carrabina-Bordoll

  • Author_Institution
    Centre Nacional de Microelectronica, CNM (CSIC), Universitat Autonoma de Barcelona, UAB, Campus UAB, Bellaterra, Barcelona, Spain
  • fYear
    1995
  • fDate
    1995
  • Firstpage
    352
  • Lastpage
    357
  • Abstract
    This paper presents a symbolic method to detect short and open circuit faults in switch-level networks. Detection and fault sensitization vector determination are possible since the behavior of each node is described by a set of two functions: the on-set and the off-set functions. Their analyses provide designers with an efficient tool for circuit verification and test pattern generation.
  • Keywords
    Analytical models; Boolean functions; Circuit analysis; Circuit faults; Circuit simulation; Electrical fault detection; Fault detection; Permission; Switching circuits; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1995. DAC '95. 32nd Conference on
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-725-1
  • Type

    conf

  • DOI
    10.1109/DAC.1995.249972
  • Filename
    1586728
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3162927