A dual-conversion zero-IF design for DVB-H RF tuner applications

This paper presents the RFIC design that uses TSMC 0.18 ¿m CMOS process to implement a DVB-H RF tuner. The design is based on a dual-conversion zero-IF architecture. Compared to the conventional up-down architecture, this adopted architecture has the advantages of no IF SAW filter but still can easily reject the image signal. To pass the protection-ratio specification, the most challenging one in DVB-H tuner specifications, this RFIC design is featured with a broadband LNA with a variable gain, a highly linear up-converting mixer with a double-balanced resistive FET architecture, and a high-linearity quadrature demodulator with the transconductance linearization technique. The important CW measured results is summarized as follows: The DC power consumption is 70.2 mW. From 50 to 860 MHz, the maximum gain varies from 19.7 to 29.2 dB with an adjustable attenuation more than 50 dB. Under the maximum-gain condition, the noise figure varies from 4.6 to 12 dB, and the OIP3 varies from 0.1 to 2.2 dBm. The CW test results agree quite well with the link-budget analysis results.