DocumentCode :
3162968
Title :
μPILRtrade package-on-package technology: development and reliability testing
Author :
Solberg, Vern
Author_Institution :
Tessera, Inc., San Jose
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
55
Lastpage :
60
Abstract :
Addressing the need for more memory capacity without increasing their products size, a number of companies have adapted various forms of multiple-die 3D packaging. A majority of these early multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer using a conventional wire-bond process. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer level yields, overall manufacturing yield of the stacked- die packaged devices have not always met acceptable levels. The motivation for developing higher density IC packaging continues to be the consumers´ expectation that each new generation of products furnish greater functionality. The challenge electronic manufactures face when competing in the world marketplace is to offer a product that will meet all physical and performance expectations of the consumer without increasing product size or cost. The information presented in this paper focuses on recent development and the results from a stringent qualification test program for the new, very thin vertically configured (stackable) μPILR package technology designed for high performance SDRAM memory products. A key advantage of this package-on-package configuration is that each layer of the package can be electrically pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functionality of the final package assembly is assured.
Keywords :
integrated circuit packaging; random-access storage; reliability; μPILR; IC packaging; SDRAM memory products; memory capacity; multiple function devices; multiple-die 3D packaging; package-on-package technology; reliability testing; sequential stacking; Consumer electronics; Costs; Electronics packaging; Integrated circuit packaging; Manufacturing; Qualifications; SDRAM; Stacking; Testing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-1324-9
Electronic_ISBN :
978-1-4244-1323-2
Type :
conf
DOI :
10.1109/EPTC.2007.4469843
Filename :
4469843
Link To Document :
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