A novel slotted-ring architecture for parallel processing: an application

A novel efficient bus architecture is presented together with an application. The bus architecture belongs to a slotted-ring class. 32-bits of data, l4-bits address, and signalling buses span across a maximum of sixteen processors configured in a ring. The bus information arriving at each processing element can be either: passed without change, captured by the processing element (PE) and/or overwritten by the PE. The delay through each PE is 30 ns when using 1989 IC technology. Through the use of newer IC technology and due to unique physical arrangement of the bus the delay time can be reduced to approximately 15 ns. Through the use of time slot arrangements and/or signalling lines the data can reach any of the other processors in the system. Logically each processor sees the memory of the other as part of a global write-only memory. The unique hardware processor internal synchronization mechanism reduces the synchronization overhead. This paper presents implementation details of the hardware as well an application in the iterative solution of dense linear equations as the test-bed multiprocessor