Architectural exploration using behavioral synthesis

One of the advantages of using the behaviour synthesis methodology is that it allows one to explore the design space at the architectural level. In this paper, we present algorithms for obtaining the design space using a behavioral synthesis tool. A branch-and-bound algorithm is given to decide the resource constraints of a process based on functional unit utilization. For multiple processes, instead of changing the resource constraints and obtaining the performance and area of the whole design each time, we analyze the performance of each process individually and then combine them using a linear time algorithm to obtain the design space graph for the overall circuit. Experimental results for both single and multiple process designs are given