Title :
Verification of ASIC designs in VHDL using computer-aided reasoning
Author :
Stabler, E.P. ; Nassif, Michael P. ; Paragi, Robert J.
Author_Institution :
Dept. of Comput. Eng., Syracuse Univ., NY, USA
Abstract :
The paper describes verification of a 32-bit processor chip using formal reasoning. The VHSIC Hardware Description Language (VHDL) code for the processor and its components have been proven to meet the formal specification which uncovered interesting specification ambiguities and design errors. The paper provides an early evaluation of the role of formal reasoning in the verification of VHDL designs of practical size
Keywords :
application specific integrated circuits; formal specification; hardware description languages; inference mechanisms; integrated circuit design; logic CAD; microprocessor chips; 32 bit; ASIC designs; VHDL; computer-aided reasoning; design errors; formal reasoning; formal specification; processor chip; specification ambiguities; Algorithm design and analysis; Application specific integrated circuits; Computational modeling; Formal languages; Formal specifications; Hardware design languages; Laboratories; Libraries; Software algorithms; Very high speed integrated circuits;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551985
