DocumentCode :
3163292
Title :
Circuit design compliance checking in VLSI circuits
Author :
Lam, Kevin N. ; Rusu, Stefan
Author_Institution :
L-Logic Design Group, Sunnyvale, CA, USA
fYear :
1996
fDate :
23-27 Sep 1996
Firstpage :
167
Lastpage :
170
Abstract :
With the ever-increasing complexity, circuit verification at the full-chip level is a major bottleneck in the design of VLSI circuits. This paper presents procedures that verify a given CMOS/BiCMOS VLSI circuit for its compliance to a set of pre-defined rules or design styles. Predefined rules range from simple connectivity and sizing rules to specific circuit topologies ensuring acceptable circuit speed, reliability, and signal integrity. Our compliance checks operate on transistor-level circuit netlists, which may contain back-annotated parasitics. The procedures and rules have been implemented in a checker called Elecdra. VLSI circuits with over 3 million devices have been successfully verified by Elecdra at the full-chip level
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; VLSI; integrated circuit design; CMOS/BiCMOS VLSI circuit; EDRA checker; Elecdra; back-annotated parasitics; circuit design compliance checking; circuit speed; circuit topology; circuit verification; connectivity rules; full-chip level; reliability; signal integrity; sizing rules; transistor-level circuit netlist; Application specific integrated circuits; BiCMOS integrated circuits; Calculus; Circuit synthesis; Circuit topology; Coupling circuits; Data structures; Design methodology; Runtime; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
ISSN :
1063-0988
Print_ISBN :
0-7803-3302-0
Type :
conf
DOI :
10.1109/ASIC.1996.551986
Filename :
551986
Link To Document :
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