Performance-driven layer assignment for printed circuit boards and integrated circuits

Performance-driven layer assignment aims at minimizing the number of vias under the timing constraints such as layer preference and path delay. A key contribution of this paper is to show that, at the stage of layer assignment, synchronous timing problems can be formulated under the Elmore delay model as linear inequalities imposed on via minimization, and via minimization can be formulated compactly as a linear integer programming problem. A solver employing both exact and heuristic solution methods has been developed. Some experimental results are included in this paper