DocumentCode :
3163349
Title :
MCM multilayer routing with layer balancing
Author :
Carothers, Jo Dale ; Liu, Tingyang ; Li, Donghui
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear :
1996
fDate :
23-27 Sep 1996
Firstpage :
179
Lastpage :
182
Abstract :
In this paper we describe an innovative layer balancing algorithm, to enhance the multichip module/dense PCB router, MCG. The MCG algorithm takes a global approach to allow candidate routes to be explored and can incorporate electrical, power and delay modeling. The layer balancing algorithm can evenly distribute nets as well as total wirelength and vias among multiple layers without increasing the number of layers. The results of testing on the standard MCM benchmarks as well as the routing results for JPL´s pathfinder decoder board are presented
Keywords :
multichip modules; network routing; JPL pathfinder decoder board; MCG algorithm; MCM multilayer routing; delay modeling; electrical modeling; layer balancing; power modeling; Benchmark testing; Crosstalk; Decoding; Delay; Internet; Multichip modules; Nonhomogeneous media; Pins; Printed circuits; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
ISSN :
1063-0988
Print_ISBN :
0-7803-3302-0
Type :
conf
DOI :
10.1109/ASIC.1996.551989
Filename :
551989
Link To Document :
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