Title :
/spl Delta/L Extraction Using Parasitic Bipolar Transistors
Author :
Wilson, D. ; Walton, A.J. ; Robertson, J.M. ; Holwill, R.J.
Author_Institution :
Univesity Of Edinburgh
Keywords :
Artificial intelligence; Bipolar transistors; CMOS process; Electrical resistance measurement; Geometry; Length measurement; Low voltage; Microelectronics; Semiconductor device modeling; Testing;
Conference_Titel :
Microelectronic Test Structures, 1988. ICMTS. Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Long Beach, CA, USA
DOI :
10.1109/ICMTS.1988.672940
