DocumentCode :
3163524
Title :
Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments
Author :
Rzepka, Sven ; Höfer, Eberhard ; Simon, Jurgen ; Meusel, Ekkehard ; Reichl, Herbert
Author_Institution :
Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
fYear :
2001
fDate :
2001
Firstpage :
704
Lastpage :
714
Abstract :
A design assessment and optimization process for wafer-level CSPs is demonstrated. Besides the basic design, the thermal stress in WLCSPs with underfill and with increased standoff height, respectively, are analyzed by FEM simulations. The results are validated and a lifetime model is calibrated by experiments. Afterwards, a WLCSP with stacked balls is optimized using the FEM models. Its total gain in lifetime over the basic design is estimated to reach 780%. WLCSP with optimum underfill even endure 10 and 20 times longer than the basic WLCSPs. Soft underfill, however, has almost no effect on the critical inelastic strain. In addition to these practical results, the paper discusses some of the risks of FEM models (such as the singularity problem) and proposes ways of avoiding or overcoming them
Keywords :
chip scale packaging; circuit optimisation; encapsulation; finite element analysis; stress analysis; thermal stresses; FEM simulations; critical inelastic strain; design optimization; lifetime model; optimum underfill; singularity problem; stacked balls; standoff height; stress analysis; thermal stress; underfill; wafer-level CSP; Analytical models; Bonding; Copper; Design optimization; Packaging; Semiconductor device modeling; Thermal expansion; Thermal stresses; Wafer scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location :
Orlando, FL
ISSN :
0569-5503
Print_ISBN :
0-7803-7038-4
Type :
conf
DOI :
10.1109/ECTC.2001.927810
Filename :
927810
Link To Document :
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