Efficient support of concurrent threads in a hybrid dataflow/von Neumann architecture

Examines the thread support in a multi-threaded processor architecture, called the Super-Actor Machine (SAM). The SAM employs a novel organization of high-speed buffer memory known as the register-cache-a memory device organized both as a register file and a cache, and is used as a buffer between the execution unit and main memory. To characterize the floating-point performance of the machine on scientific benchmarks, a new performance measure is introduced, called the Floating-point Arithmetic and logic operations per machine Beat, or FAB for short. Results from a detailed simulation are very encouraging: for the memory-intensive SAXPY scientific loop, a processing element of the SAM can attain a .85 FAB rating as compared to a value of nearly 1 for the IBM RS/6000 which employs the combined floating-point add-multiply operation (this type of instruction has not been implemented on the SAM yet). Furthermore, the SAM can attain this rating with less execution resources (i.e. high-speed registers) than typical multi-threaded architectures