DocumentCode :
3163565
Title :
A 400 megasample per second digital receiver ASIC
Author :
Inkol, Robert ; Szwarc, Valek ; Desormeaux, Luc ; Esonu, Mike ; Al-Khalili, Dhamin
Author_Institution :
Defence Res. Establ., Ottawa, Ont., Canada
fYear :
1996
fDate :
23-27 Sep 1996
Firstpage :
235
Lastpage :
238
Abstract :
An application specific integrated circuit has been designed to perform digital quadrature demodulation and other signal processing functions on digitized IF data in electronic warfare receivers. A fully pipelined, parallel architecture implemented on a GaAs gate array permits a nominal sampling rate of 400 megasamples per second. At this sampling rate the -3 dB bandwidth exceeds 80 MHz
Keywords :
III-V semiconductors; application specific integrated circuits; demodulation; digital signal processing chips; electronic warfare; gallium arsenide; military equipment; parallel architectures; pipeline processing; receivers; telecommunication computing; 80 MHz; EW receivers; GaAs; GaAs gate array; application specific integrated circuit; digital quadrature demodulation; digital receiver ASIC; digitized IF data; electronic warfare receivers; fully pipelined parallel architecture; signal processing functions; Application specific integrated circuits; Array signal processing; Bandwidth; Demodulation; Digital signal processing; Electronic warfare; Gallium arsenide; Parallel architectures; Signal design; Signal sampling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
ISSN :
1063-0988
Print_ISBN :
0-7803-3302-0
Type :
conf
DOI :
10.1109/ASIC.1996.552001
Filename :
552001
Link To Document :
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