• DocumentCode
    3163577
  • Title

    Testing in a mixed-signal world

  • Author

    Agrawal, Vishwani D.

  • Author_Institution
    AT&T Bell Labs., Murray Hill, NJ, USA
  • fYear
    1996
  • fDate
    23-27 Sep 1996
  • Firstpage
    241
  • Lastpage
    244
  • Abstract
    Wide differences in test signals used for analog and digital circuits make a common test for a mixed-signal device difficult. A divide and conquer strategy partitions the circuit into three types of blocks: analog, digital logic and memory. A design for testability structure using boundary scan and analog test bus allows very effective test application. With this design, separate specialized tests are applied to analog and digital parts, as well as to interconnects. While the partitioned architecture provides a reasonable test solution, weakness remains in the test of block interfaces. Research on unified analog-digital tests is recommended. Delay tests and current measurement tests might be possible candidates
  • Keywords
    boundary scan testing; built-in self test; design for testability; integrated circuit testing; mixed analogue-digital integrated circuits; BIST; DFT structure; analog test bus; analog-digital circuits; boundary scan; current measurement tests; delay tests; design for testability; divide/conquer strategy; mixed-signal circuits; partitioned architecture; unified analog-digital tests; Analog circuits; Analog-digital conversion; Circuit faults; Circuit testing; Electronic equipment testing; Frequency; Integrated circuit interconnections; Logic testing; Pulse amplifiers; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • ISSN
    1063-0988
  • Print_ISBN
    0-7803-3302-0
  • Type

    conf

  • DOI
    10.1109/ASIC.1996.552002
  • Filename
    552002