DocumentCode
3163585
Title
An architectural design of a wavelet coprocessor
Author
Langi, A. ; Kinsner, W.
Author_Institution
Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
fYear
1994
fDate
25-28 Sep 1994
Firstpage
497
Abstract
A flexible but fast and area-efficient VLSI architecture of a coprocessor to perform the discrete wavelet transform (DWT) can be designed using the pyramidal algorithm, pipelined data path unit, direct memory access, and a single 16-bit integer multiplier and adder/subtracter. A design of a 64-point, 4-coefficient Daubechies DWT is described
Keywords
VLSI; coprocessors; digital signal processing chips; pipeline processing; signal processing; wavelet transforms; 16 bit; Daubechies DWT; adder/subtracter; architectural design; area-efficient VLSI architecture; direct memory access; discrete wavelet transform; pipelined data path unit; pyramidal algorithm; signal processing; single 16-bit integer multiplier; wavelet coprocessor; Coprocessors; Digital signal processors; Pipeline processing; Signal processing; Very-large-scale integration; Wavelet transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on
Conference_Location
Halifax, NS
Print_ISBN
0-7803-2416-1
Type
conf
DOI
10.1109/CCECE.1994.405797
Filename
405797
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