Circuit partitioning for distributed VHDL fault simulation

Switch-level faults, as opposed to traditional gate-level faults can more accurately model physical failures found on an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing distributed switch-level fault simulation using a novel switch-level circuit partitioning technique. Transistor reverse level order circuit partitioning is shown to produce groups of transistors that share fan-in at nodes. Using this partitioning technique, results show that distributed switch-level fault simulation achieves increased speed-up over distributed switch-level fault simulation using random fault set partitioning techniques