Title :
An efficient path-delay fault simulator for mixed level circuits
Author :
Kang, Yong Seok ; Yim, Yong Tae ; Kang, Sungho
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
This paper describes a path delay fault simulator for standard scan environments and introduces a new algorithm using new logic values in order to enlarge the scope of a path delay fault simulation to the CMOS designs. A new simulator can deal with mixed level circuits. Considering switch level devices, this simulator can treat delay faults more closely to their electrical behavior. The results prove the efficiency of the simulator
Keywords :
CMOS logic circuits; VLSI; application specific integrated circuits; automatic test software; circuit analysis computing; delays; fault diagnosis; integrated circuit testing; logic testing; CMOS designs; mixed-level circuits; path-delay fault simulator; standard scan environments; switch-level devices; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Delay; Robustness; Switches; Timing; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.552007
