Edelstein - Invited Speaker

Summary form only given: This talk will present a broad and detailed discussion of technical issues facing advanced Cu/low-k and /ULK BEOL technologies, and potential solutions being worked on to address them. Of particular focus will be the relationship between integration and reliability for the issues. Some key metallization, dielectric, and packaging elements will be addressed. Today, work has begun on the 22 nm CMOS node (35 nm half-pitch wiring), which represents our 8th full-node Cu BEOL generation, and a 1/10x scaling from our original introduction. For fine Cu wires on high-performance logic chips, scaling phenomena have led to a crossover at 32 nm node of process/reliability margins below technology needs. This raises the need for changes to the wiring structure and materials. Whereas some of these changes have been exploratory in the past, they may now be essential. For example, selective metal caps, Cu-alloy dopants, and/or noble metal liner components may be required to maintain an open process/reliability window. These changes may also bring new detriments relative to the near-ideal PVD TaN/Ta/Cu liner/seed and dielectric barrier cap solution of previous nodes. The BEOL insulator has evolved during this time-span, from SiO₂ with k = 4.1 through various increments down to porous SiCOH with k = 2.2, and to airgaps with k=1.0. (The corresponding effective dielectric constants have migrated from 4.3 to 2.5, and to 2.0, respectively). Significant learning in interfaces, mechanics, and material + interface optimizations have helped solve BEOL mechanical and chip-packaging problems for successively weaker and more brittle insulators, to survive large packaging-induced tensile stresses on the chip terminals and periphery. This area of engineering has been an essential enabler to the successful manufacturing of large packaged chips containing ultralow-k BEOL insulators.