Title :
Low-power digital PLL with one cycle frequency lock-in time for clock syntheses up to 100 MHz using 32,768 Hz reference clock
Author_Institution :
Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Zurich, Switzerland
Abstract :
A low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level
Keywords :
CMOS digital integrated circuits; digital phase locked loops; jitter; timing circuits; 100 MHz; 32768 Hz; clock frequencies; lock-in time; low-power digital PLL; power management; reference clock; Clocks; Costs; Energy management; Frequency conversion; Frequency synthesizers; Jitter; Oscillators; Phase locked loops; Power generation; Power system management;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.552013
