Title :
Low-power design technique for ASICs by partially reducing supply voltage
Author :
Usami, Kimiyoshi ; Ishikawa, Takashi ; Kanazawa, Masahiro ; Kotani, Hiroko
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing one to reduce power without performance degradation. As a result of application to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing became less effective. The CVS is considered to be a key technique toward the deep sub-micron age, in which the wire capacitance will be further dominant
Keywords :
application specific integrated circuits; capacitance; integrated circuit design; logic arrays; logic design; clustered voltage scaling; gate resizing; low-power ASIC; low-power design technique; power reduction; supply voltage partial reduction; wire capacitance; Application specific integrated circuits; Capacitance; Combinational circuits; Degradation; Information systems; Latches; Logic; Timing; Voltage; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.552015
