Reducing power dissipation in low voltage flash memories

Author

Luderman, Brenda L. ; Chang, Kuo-Tung ; Su, Jeffrey ; Cavins, Craig ; Pabst, John ; Yu, Tat-kwan ; Higman, Jack

Author_Institution

Semicond. Products Sector, Motorola Inc., Austin, TX, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

305

Lastpage

308

Abstract

A new low voltage flash circuit model is presented. This SPICE model is used to identify techniques for reducing the average power dissipated in a flash memory during a programming cycle. The AND flash memory cell is used in this analysis. For a selected bitcell in a NOR block, the power dissipated is dominated by a band-to-band transient current. SPICE simulations show that this power can be reduced by decreasing the charge pump´s slew rate and the erase threshold voltage. In an unselected bitcell, the power dissipated is the sum of band-to-band and drain charging currents. Simulations show that this power can be reduced by increasing the positive word line bias applied to unselected bitcells in the NOR block

Keywords

EPROM; PLD programming; SPICE; circuit analysis computing; equivalent circuits; integrated circuit modelling; integrated memory circuits; leakage currents; tunnelling; AND flash memory cell; LV flash circuit model; NOR block; SPICE model; SPICE simulations; band-to-band transient current; charge pump slew rate; drain charging current; erase threshold voltage; low voltage flash memories; positive word line bias; power dissipation; programming cycle; unselected bitcells; Charge pumps; Circuit simulation; Electrons; Flash memory; Lifting equipment; Low voltage; Power dissipation; SPICE; Semiconductor device measurement; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.552016

Filename

552016