A Partitioning-based Logic Optimization Method for Large Scale Circuits with Boolean Matrix

This paper presents a new logic partitioning method for optimizing large scale circuits. The proposed method partitions a given circuit into transitive fanin-disjoint sub-circuits by matrix operations, so that various optimization methods can be applied to each partitioned sub-circuit instead of the whole circuit. Experimental results show that the proposed method achieves high-quality design comparable to the one optimized for the whole circuits, with much shorter time(1/20). Thus, the circuits with over 10,000 gates can be optimized by the proposed partitioning.