Low power design of two-dimensional DCT

Author

Li, Jim ; Lu, Shih-Lien

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

fYear

1996

fDate

23-27 Sep 1996

Firstpage

309

Lastpage

312

Abstract

This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8×8 2D DCT built with two 1D DCT employing these techniques is designed. The estimated power consumption for this 8×8 2D DCT is 16.95 mW

Keywords

application specific integrated circuits; data compression; digital signal processing chips; discrete cosine transforms; integrated circuit design; logic design; 1.5 V; 16.95 mW; 20 MHz; 2D DCT design; 2D discrete cosine transform; ASIC; DCT coefficients; DSP chip; constant-multipliers; low power design; low-voltage operation; power consumption; transition probability; two-dimensional DCT; Adders; Circuits; Clocks; Computer architecture; Discrete cosine transforms; Energy consumption; Image coding; Libraries; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-3302-0

Type

conf

DOI

10.1109/ASIC.1996.552017

Filename

552017