• DocumentCode
    3163874
  • Title

    3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory

  • Author

    Liu, Haitao ; Groothuis, Steve ; Mouli, Chandra ; Li, Jian ; Parat, Krishna ; Krishnamohan, Tejas

  • Author_Institution
    Dept. of Process R&D, Micron Technol. Inc, Boise, ID
  • fYear
    2009
  • fDate
    3-3 April 2009
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A new Technology CAD (TCAD) methodology has been applied to accurately extract cell-cell interference. The new method uses a "DeltaVt ratio" model instead of the conventional "capacitance ratio" model. The new method will be introduced and validated by recent experimental data. The predictions of the cell-cell interference on sub-40 nm floating gate (FG) cells and charge trapped flash (CTF) cells will be discussed. Finally, the implications and challenges of Multilevel Cell (MLC) applications will be made.
  • Keywords
    NAND circuits; flash memories; 3D simulation study; advanced NAND flash memory; cell-cell interference; charge trapped flash; floating gate cells; size 40 nm; technology CAD methodology; Capacitance; Character generation; Conducting materials; Data mining; Interference; Nonvolatile memory; Research and development; Silicon; Switches; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electron Devices, 2009. WMED 2009. IEEE Workshop on
  • Conference_Location
    Boise, ID
  • Print_ISBN
    978-1-4244-3551-7
  • Electronic_ISBN
    978-1-4244-3552-4
  • Type

    conf

  • DOI
    10.1109/WMED.2009.4816143
  • Filename
    4816143
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3163874