A Self-Adaptive and PVT Insensitive Clock Distribution Network Design for High-Speed Memory Interfaces

A clock distribution network (CDN) insensitive to process, voltage, and temperature (PVT) variations is presented in this paper. Unlike a traditional source-synchronous interface, the CDN uses a current-mode logic (CML) divider and sense- amp-based data receiver for data capture and deserialization. The proposed input path extends its operating range beyond 4- Gb/s/pin without the need for retraining. A unique self-adaptive bias generator based on a Bandgap reference is also disclosed. Simulation data based on the CDN shows a 40% reduction in timing sensitivity for a 100 mV supply voltage change and an 85degC temperature change at 4-Gb/s using a 3-metal, 50-nm DRAM process. Design considerations are also addressed based on power, performance, and complexity.