DocumentCode :
3163986
Title :
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard cells
fYear :
1995
fDate :
1995
Firstpage :
702
Lastpage :
706
Abstract :
The possibility of determining the accurate worstcase timing performance of a library of standard cells is of great importance in a modern VLSI structured semicustom IC design flow. The margin for profitability is indeed extremely tight because of the ever increasing performance demand which can hardly be satisfied by a corresponding progress of the process technology. It is therefore of utmost importance to avoid excessively pessimistic estimates of the actual cell performance in order to exploit all the potential of the fabrication process. In this paper it is described a technique that allows to determine the worst-case points with an assigned probability value. It is thus possible to select the desired level of confidence for the worst-case evaluation of digital IC designs with good accuracy. The results of the Assigned Probability Technique (APT) are presented and compared with those obtained by standard methods both at cell and at circuit level showing the considerable benefits of the new method.
Keywords :
Circuit optimization; Circuit simulation; Distributed computing; Fabrication; Microelectronics; Permission; Profitability; Software libraries; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.250055
Filename :
1586792
Link To Document :
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