Clock tree regeneration

Author

Ho, Jan-Ming ; Tsay, Ren-Song

Author_Institution

Inst. of Inf. Sci., Acad. Sinica, Taipei, Taiwan

fYear

1992

fDate

28-29 Feb 1992

Firstpage

198

Lastpage

203

Abstract

The authors present a clock tree regeneration algorithm for improving both the wirability and performance of VLSI chip designs. After circuit placement, they modify the clock trees originally specified by logic designs utilizing the geometrical information derived from the placement. First, a bipartite bottleneck matching approach is applied to minimize the longest driver to clock pin length. Then a linear assignment approach is used to optimize the total driverpin length. The experimental results are extremely encouraging

Keywords

VLSI; circuit layout CAD; clocks; trees (mathematics); bipartite bottleneck matching approach; circuit placement; clock tree regeneration algorithm; linear assignment approach; logic designs; performance; wirability; Clocks; Delay; Driver circuits; Logic; Neck; Optimization; Pins; Routing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1992., Proceedings of the Second Great Lakes Symposium on

Conference_Location

Kalamazoo, MI

Print_ISBN

0-8186-2610-0

Type

conf

DOI

10.1109/GLSV.1992.218345

Filename

218345

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3163990