DocumentCode
3164027
Title
A distributed reconfiguration algorithm for an array of processors
Author
DeBrunner, Linda S. ; Gray, F. Gail
Author_Institution
Virginia Polytech. & State Univ., Blacksburg, VA, USA
fYear
1990
fDate
1-4 Apr 1990
Firstpage
452
Abstract
A reconfiguration strategy for an array of processors is discussed. The White-Gray fault-tolerant array architecture, an array of processors with connections to the cells that are two cells away in the east and west directions as well as to eight nearest neighbours, is briefly discussed. The authors generalize the Yanney-Hayes distributed recovery strategy to the White-Gray array architecture. Some guidelines for designing an algorithm based on the Yanney-Hayes strategy are presented. Simulation results and proofs of the algorithm´s correctness are summarized
Keywords
distributed processing; fault tolerant computing; parallel architectures; White-Gray fault-tolerant array architecture; Yanney-Hayes distributed recovery strategy; array of processors; correctness; distributed reconfiguration algorithm; nearest neighbours; proofs; simulation results; Algorithm design and analysis; Computational modeling; Computer architecture; Distributed algorithms; Distributed computing; Fabrication; Fault tolerance; Nearest neighbor searches; Runtime; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Southeastcon '90. Proceedings., IEEE
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/SECON.1990.117854
Filename
117854
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