DocumentCode :
3164046
Title :
A Design and Validation System for Asynchronous Circuits
Author :
Peter Vanbekbergen, Albert Wang, Kurt Keutzer
Author_Institution :
Synopsys, Inc., Mountain View, CA
fYear :
1995
fDate :
1995
Firstpage :
725
Lastpage :
730
Abstract :
In this paper we present a completemethodology for the design and validation of asynchronous circuits starting from a formal specificationmodel that roughly correspondsto a timing diagram. The methodology is presented in such a way that it is easy to embed in the current methodology for synchronous circuits. The different steps of the synthesis process will just be briefly touched upon. The main part of the paper concentrates on the simulation and validation of asynchronous circuits. It discusses where the designer needs validation and how it can be done. It also explains how this process can be automated and embedded in the complete methodology.
Keywords :
Asynchronous circuits; Circuit simulation; Circuit synthesis; Clocks; Control system synthesis; Design methodology; Formal specifications; Microelectronics; Synchronization; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.250059
Filename :
1586796
Link To Document :
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