Title :
An alternative algorithm for high speed multiplication and addition using growing technique
Author_Institution :
Dept. of Electr. Eng., Northern Illinois Univ., De Kalb, IL, USA
Abstract :
An alternative algorithm is presented for multiplication/addition of variable bit-size operands. The algorithm is shown to be fast, and the computational time is variable and dependent on the accuracy requested. The growing nature of the product term, during the course of operation, gives the method some unique computational properties. The algorithm is implemented for the design of 32×32-bit multiplier
Keywords :
digital arithmetic; multiplying circuits; high speed multiplication; multiplier; variable bit-size operands; Algorithm design and analysis; Clocks; Counting circuits; Digital filters; Digital integrated circuits; Hardware; Manipulator dynamics; Timing;
Conference_Titel :
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2610-0
DOI :
10.1109/GLSV.1992.218355
