Title :
Design considerations for a bipolar implementation of SPARC
Author :
Agrawal, A. ; Brown, E.W. ; Petolino, J. ; Peterson, James R.
Author_Institution :
Sun Microsyst. Inc., Mountain View, CA, USA
fDate :
Feb. 29 1988-March 3 1988
Abstract :
The design of Sun Microsystems´ Scalable Processor Architecture (SPARC) using bipolar emitter-coupled-logic (ECL) process is considered. The BIT1 ECL process and design considerations for an ECL implementation of SPARC are described. Bus structures, cache concerns, interface considerations, and power density are discussed.<>
Keywords :
bipolar integrated circuits; computer architecture; emitter-coupled logic; microprocessor chips; BIT1; SPARC; Scalable Processor Architecture; bipolar emitter-coupled-logic; bipolar implementation; bus structures; cache concerns; interface considerations; power density; CMOS technology; Costs; Integrated circuit noise; Microprocessors; Power transmission lines; Propagation delay; Silicon; Sun; Wiring; Working environment noise;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4817
